Let us go through a simple example to illustrate the test development process. Consider a simple NAND gate device below with inputs A, B and output Q. We can call these I/O pins. We also have a pin for the power supply, Vdd and a pin for ground, Gnd.
Fig.1 A 4-NAND IC(1)
Fig.1 A NAND gate symbol/schematic
Obviously, we want to test the NAND functionality against the truth table, applying the logic levels to the inputs and checking the output. However, we also have to do more tests as part of checking the manufacturing process. These are called parametric tests. But first, let's map the DUT to the Tester resources.
The test software development toolkit will include a channel map to indicate the tester-DUT mapping. In our simple example, we will consider the 4 NAND gates in the IC as 4 sites for multi-site testing. We will assign each site to a separate slot (group) of digital channels. For example, channel map entry 1.ch2 indicates tester slot 1, channel 2. In actual practice, testers have several hundred digital channels, so we could easily test many quad-NAND ICs in parallel.
We begin by testing the ESD (Electro-Static Discharge) protection diode structure in the device. This is called a Continuity test because it allows us to test if there is a open or a short inside the device that was caused during manufacturing.
On each of the I/O pins, we have a diode each connecting to Vdd and Gnd. The purpose of these diodes is to protect the internal device circuitry in case of ESD and pass the current through to either supply or ground. The goal is to test for the existence of each of these diodes. The voltage drop through a forward-biased diode is ~0.6v.
We need to connect and set the supply pin, Vdd = 0v. The tester digital pin electronics is connected to the I/O pin. Because we need to measure the diode voltage drop, we will use the PMU(Parametric Measurement Unit) which is part of the pin electronics available at each pin.
We can test for adjacent pin to pin shorts by forcing a logic high on all even pins and 0v on all odd pins and then forcing a logic high on all odd pins and 0v on all even pins. We can read the current being pulled or pushed at each pin and since all pins should be isolated from each other, we will know if there is a current path from one pin to another causing a leaky path or a short.
Note that we have not powered up the DUT so far. We need to test if any of the power circuits on the DUT are shorted and power it up gracefully. The designer may recommend a power up sequence for multiple power supplies on the DUT. In this test:
In the DUT, we could have leaky transistors, vias etc. To detect these, we increase Vdd to the max rating, to exercise any leaky paths. If we have digital I/Os, we must first get these pins to an input state. This is usually accomplished by a pattern. We drive all inputs to the logic high and measure the current being pulled at each pin (Iih). We repeat this taking all input to 0v and measure the current being pushed by the DUT (Iil).
A tester digital pattern is essentially a truth table where we control the logic states of the inputs and test the logic states on the output. For our NAND example the pattern may look like:
To test the above pattern, we need to set voltage levels for logic levels 0,1 on the input pins. These are called Vil and Vih respectively. We also need to set voltage levels to test for logic L, H on the output pins. These are called Voh and Vol repectively. For example, we may set:
In real applications, the DUT output may be required to drive a certain load, i.e the DUT output must be able to sutain the voltage on the output at Voh while driving the load current. This current is called Ioh. Conversely, the DUT must be able to sustain the outpur at Vol while current is being pushed into it by the load. This current is called Iol. The pin electronics provides a programmable active load, so we can set Ioh and Iol during the pattern test. For example, we may set:
We also need to specify the timing for each of the vectors in the tester pattern. This includes the time-period/cycle for each row in the pattern, the time instant within the cycle when the tester should drive the input(s) to the Vih/Vil levels, the time instant when the output(s) are expected to change and be stable, so the comparator/receiver inside the pin-electronics can check for the Voh/Vol levels. For example, we may set:
We increase Vdd to the max rating and measure the current the device pulls from the supply while running functional tests.