PLLs with reference clock inputs and divided outputs
Power management blocks such as LDOs and Switchers
High-speed digital PCIe, USB, DDR buses
Analog voltage/current reference inputs for internal circuits
Other digital GPIOs (General purpose I/Os)
This is a fairly complex yet common scenario in present day SOCs. Consider the following challenges:
Critical Components: Components such as decoupling caps for power supplies, resistors for current reference inputs, inductors for switching power supplies, isolation resisters, xtal for PLL reference inputs have to be placed close to the DUT.
Pin/Ball Arrays: In BGAs and WCSP type packages, densely packed ball arrays with low pitch between solder balls makes it hard to route traces out from the pads on the top layer. Careful consideration must be given to prevent crosstalk and noise from adjacent traces. Micro-vias are sometimes used to drop-down to an inner layer and then route signals further.
Relays: There may be a need to multiplex tester resources to some pins to test different parameters. This may aslo be because some pins on the DUT may serve multiple purposes in different modes. This requires mechanical relays, which tend to take up relatively large areas (we may not be able to use relatively smaller electronic switches due to continuity testing requirements because we may end up testing the ESD diodes on the electronic switch instead).
Multi-site Placement:For multi-site boards, especially probe cards, the DUT sites must be kept in close spacing to match probe/handler requirements minimizing available space around them.
Test planning and design of the DIB is started along side the IC physical design phase, but it can only be released to fabrication after DUT tapeout as there may be last minute design/pinout changes on the DUT that will affect the DIB. Typically, we plan to have the board in-house a week before silicon arrives (4-6 weeks) because we must validate the DIB prior to silicon debug. The tight window on both ends necessitates careful planning. PCB manufacturers offer expedited processes at higher costs if required.
Test Hardware Design/Build Plan (4-6 weeks):
Schematic Design (2-3 weeks)
Layout Design (post tapeout, 2 weeks)
Fabrication (2 weeks) (may be fabricated to have 20-30 layers)