Test Hardware Design

Device Interface Board design

Let's say you have to design a DIB for a SOC that includes:

This is a fairly complex yet common scenario in present day SOCs. Consider the following challenges:

Test planning and design of the DIB is started along side the IC physical design phase, but it can only be released to fabrication after DUT tapeout as there may be last minute design/pinout changes on the DUT that will affect the DIB. Typically, we plan to have the board in-house a week before silicon arrives (4-6 weeks) because we must validate the DIB prior to silicon debug. The tight window on both ends necessitates careful planning. PCB manufacturers offer expedited processes at higher costs if required.

Test Hardware Design/Build Plan (4-6 weeks):

  1. Schematic Design (2-3 weeks)
  2. Layout Design (post tapeout, 2 weeks)
  3. Fabrication (2 weeks) (may be fabricated to have 20-30 layers)
  4. Component Assembly (1 week)
  5. Probe Assembly (1 week)

Schematic Design

Layout Design

  1. Component Placement
  2. Layer Stackup
  3. Analog/RF Routing
  4. High-Speed Digital Routing
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