A typical SOC tester has the following instrumentation that is programmable for DUT specifications.
Devices are placed inside sockets/contactors. These come with lids with clamps for hand-testing. The lids are removed during automated testing and a robotic handler inserts and picks up the devices from the sockets (pick-and-place). Another way is to load devices in plastic sleeves and use a gravity-fed handler. For probe test, the probe tips in the sockets make contact with the pads on the die on a wafer. By multi-site testing we mean that the test fixture accomodates multiple devices(sites) which are the tested in parallel. For example, we may be 4 or 8 or 16 sites per insertion.
ICs are built on a wafer and we often test them on the wafer before cutting into individual die. This is referred to as wafer probe. Probe tips from the probe card (test fixture) extend out to make electrical contact with the pads on the individual die. The wafer sits on a chuck which is moved very precisely by a stepper motor. The pads on the die are positioned to make contact with the probe tips on the test fixture. A high-magnification camera is used for fine adjustment and alignment of the wafer and the probe tips on the test fixture
After is the wafer is cut into individual die, these may be attached to a leadframe with pins which is finally encapsulated in epoxy/plastic.
Newer WCSP (Wafer Chip-Scale Package)/flip-chip devices are only tested at probe. These devices are not encapsulated with leadframes. Instead, solder balls are mounted under the wafer, and they are sold as die or by wafer. The WCSP package is directly mounted onto PCBs.
After assembly and before shipping to customer, the package test is often referred to as Final Test (FT). Handlers and probers allow for temperature control during testing and communicate pass pass/fail data to the host PC over GPIB.
When the test fixture is mounted on the test head, electrical contacts connect to the tester resources (at the edges of the test fixture). We route traces on the test fixture(PCB) to connect to the DUT(s) in the center.
We design the test fixture to connect the I/O pins of the DUT to the digital channels of the tester and then setup the DUT-to-Tester channel map in the test program. The digital channel on the tester typically has dedicated drivers and comparators/receivers that can be connected to each pin of the DUT. These can be used to check the drive logic states on the inputs and compare the logic levels on the inputs. In addition the pin electronics may have PMUs (Parametric Measurement Units) for each pin of the DUT. These can be programmed to voltage and current values to bias or measure the DUT I/O pins. Each digital channel has a unique identifer that we use to indicate the connection in the test program. The channels may be grouped into slots.
There are a limited number of power supplies available from the tester that can be used to power up the DUT. These have meters associated with them to measure current consumed by the DUT. The power supplies may be connected to the DUT using thick PCB traces or power planes inside the test fixture PCB. Each tester power supply has a unique identifer that we use in the test program to indicate the connection to the DUT pin.